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1 . To understand the right way to describe fundamental circuits using VHDL
2 . To make and replicate a VHDL text file
3. To understand how to give pins to get a desired routine to the eSOC II board
4. To download a plan to the eSOC II panel and check that the developed circuit functions as designed
II. REFERENCE TABLE
APPLE PC or Compatible with Windows 2000 or more
Quartus 2 Design Computer software – Edition 9. 1
eSOC II Board
The circuit style for this Laboratory is entered using Computer Aided Anatomist (CAE) design and style tools pertaining to Altera's programmable logic family. These tools permit the complete design, compilation, ruse, verification, and programming of a programmable common sense IC to become done in one simple, user-friendly design environment. The first thing is to enter the design for processing, called DESIGN ACCESS. This is usually required for two different methods. The 1st way is named schematic capture and requires a schematic pertaining to the common sense design. The schematic uses graphical emblems to represent common sense gates and functions, that are connected employing graphical cables similar to Electronic digital Work Table. The second approach to DESIGN ENTRY is to use a specialized development language called VHDL (Very high-speed bundled circuit Hardware Description Language). This method is employed in this and future Labs. The next step is to COMPILE the structure. This creates a design netlist that describes the interconnections between entrance and IO pins and routes these connections within the programmable common sense IC. The logic style is reduced (reduced) and any system errors are shown. The COMPILE likewise generates timing files used in the ruse and coding files used to plan the nick. The next step is to SIMULATE the logic design. This is a verification step used to analyze the functionality of the design. Ruse allows all of us the chance of verifying a design devoid of actually building the signal. The ruse is accomplished and the result values may be observed as the insight values changes. After the design has been joined, compiled and simulated, we all check leads to see if the design needs to be changed, recompiled, and simulated. If perhaps not, we are able to proceed to the last step and PLAN the PLD. For this step, we utilize DeVry eSOC III table. The eSOC III (electronic System-on-a-Chip) table is designed to enable a direct software to the Altera Cyclone 3 EP3C16Q240C8 FPGA. The board provides an program to the chip, along with supporting user interface hardware. Specifics about the construction and use of the eSOC III board are available in the eSOC III Users Guide supplied with the plank. The following is a summary of data taken from that Guide. The eSOC III board is demonstrated in Figure 1 . 1 (from the person Guide coming from Arches Calculating Systems). The board contains the Altera FPGA (in the center), a 24 Megahertz clock supply (U8 left of the FPGA), and numerous suggestions switches and output shows.
Figure 1 . you: eSOC III Board
There are two sorts of insight switches—single-pole-single-throw (SPST) toggle changes (S1 and S2) and debounced push-button (SPST) changes (DB0 and DB1). The output features include red LEDs (RD0 – RD7), green LEDs (GR0 – GR7) and two seven-segment displays (Digit0 and Digit1). The FPGA utilizes a random access memory (RAM) technology. This will likely be explained in a after course. For the time being, the key strategy is that a plan is stored and taken care of only as long as the power can be applied (such a doc you miss to save, the information disappears if the power is definitely removed). Because of this every time the eSOC III board is turned off, this software in the FPGA is misplaced. IV. METHOD
A. VHDL Text Data file Entry and Compilation
1 . Open the Quartus 2 Main Windows (Figure 1 . 2).
Determine 1 . a couple of: Quartus II Main Windowpane
2 . Quartus treats all designs while projects. The best method to begin a project is by using a sorcerer within Quartus. Select Make a New Task (New Job...